Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software
Cited by
8 articles.
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1. A High Performance Scan Flip-Flop Design for Serial and Mixed Mode Scan Test;IEEE Transactions on Device and Materials Reliability;2018-06
2. A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2017
3. A New Scan Flip Flop Design to Eliminate Performance Penalty of Scan;2015 IEEE 24th Asian Test Symposium (ATS);2015-11
4. Eliminating the Timing Penalty of Scan;Journal of Electronic Testing;2013-02
5. Scan to Nonscan Conversion via Test Cube Analysis;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2013-02