A digitally-calibrated 2-stage cyclic ADC for a 33-Mpixel 120-fps Super High-Vision CMOS image sensor
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6971895/6984913/06984934.pdf?arnumber=6984934
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Nonlinear error analysis and calibration model for cyclic ADCs in large array CMOS image sensors;Microelectronics Reliability;2021-02
2. A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-01
3. A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05
4. A Two-Step Prediction ADC Architecture for Integrated Low Power Image Sensors;IEEE Transactions on Circuits and Systems I: Regular Papers;2017-01
5. Precise and High-Speed Technique of Digital Calibration for Column-Parallel Two-Stage Cyclic ADC Suitable for 33-Mpixel 120-fps CMOS Image Sensor;IEEJ Transactions on Sensors and Micromachines;2017
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