IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language-Reference-Cited by-同舟云学术

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IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language

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IEEE

Cited by 44 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Advanced UVM-Based Verification Methodology for Consumer Electronics HW Design Evaluation and Validation;2024 Zooming Innovation in Consumer Technologies Conference (ZINC);2024-05-22

2. Hardware Realization of High-Speed Area-Efficient Floating Point Arithmetic Unit on FPGA;2024 International Conference on Machine Intelligence and Smart Innovation (ICMISI);2024-05-12

3. Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

4. Real-Time Graph Building on FPGAs for Machine Learning Trigger Applications in Particle Physics;Computing and Software for Big Science;2024-03-21

5. Translation of Semi-extended Regular Expressions Using Derivatives;Lecture Notes in Computer Science;2024

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