Deploying Artificial Intelligence in Design Verification to Accelerate IP/SoC Sign-off with Zero Escape
Author:
Affiliation:
1. Birla Institute of Technology & Science, Pilani, K.K. Birla,Dept. of Electrical & Electronics Engg.,Goa,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10595550/10595552/10595855.pdf?arnumber=10595855
Reference13 articles.
1. Functional Verification Measures to Challenge State Retention Strategy for Inaccessible Power-Gating of Low Power IPs
2. IEEE Standard for SystemVerilog--Unified Hardware Design, Specification, and Verification Language;IEEE Std 1800-2017 (Revision of IEEE Std 1800-2012),2018
3. IEEE Standard for Universal Verification Methodology Language Reference Manual;IEEE Std 1800.2-2020 (Revision of IEEE Std 1800.2-2017),2020
4. IP Transformation Initiatives to Generate Scalable Functional Verification Collaterals for Smart Reusability and Reduced Effort for Sign-off
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