Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors
Author:
Affiliation:
1. National Taiwan University,Department of Electrical Engineering,Taiwan
2. Graduate Institute of Electronics Engineering
Funder
Ministry of Science and Technology
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9808359/9808467/09808811.pdf?arnumber=9808811
Reference21 articles.
1. Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study
2. An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
3. Reinforcement-Learning-Based Test Program Generation for Software-Based Self-Test
4. Software-based self-testing methodology for processor cores
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1. Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test;2024 IEEE European Test Symposium (ETS);2024-05-20
2. Branch-Aware Self-Test Program Generation for Processor Cores;2024 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA);2024-04-22
3. BDD-Based Self-Test Program Generation for Processor Cores;2023 IEEE International Test Conference in Asia (ITC-Asia);2023-09-12
4. Test Response Compaction for Software-Based Self-Test;2022 IEEE International Test Conference in Asia (ITC-Asia);2022-08
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