Clock-deskew buffer using a SAR-controlled delay-locked loop-Reference-Cited by-同舟云学术

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Clock-deskew buffer using a SAR-controlled delay-locked loop

Published:2000-08 Issue:8 Volume:35 Page:1128-1136
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Guang-Kaai Dehng ,June-Ming Hsu ,Ching-Yuan Yang ,Shen-Iuan Liu

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/18654/00859501.pdf?arnumber=859501

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4. Design of a Low-Power Linear SAR-Based All-Digital Delay-Locked Loop;2019 27th Iranian Conference on Electrical Engineering (ICEE);2019-04

5. Impact of Bias Temperature Instability (BTI) Aging Phenomenon on Clock Deskew Buffers;Journal of Electronic Testing;2019-03-19

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