1. A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM
2. B. Kim, T. Weigandt, and P. Gray, PLL/DLL system noise analysis for low jitter clock synthesizer design, in Proc. IEEE Int. Symp. on Circuits and Systems, vol. 4, pp. 31-35, May 1994.
3. A variable delay line PLL for CPU-coprocessor synchronization
4. A semidigital dual delay-locked loop
5. R. Kreienkampet al., A 10-Gb/s CMOS clock and data recovery circuit with an analog phase interpolator, in Proc. IEEE Custom Integrated Circuits Conf., pp. 73–76, Sept. 2003.