Efficient Implementation of a Fully Analog Neural Network on a Reconfigurable Platform
Author:
Affiliation:
1. School of Eletrical and Computer Engineering, Georgia Institute of Technology,Atlanta,GA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10405424/10405847/10405875.pdf?arnumber=10405875
Reference6 articles.
1. A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity
2. Integrated Floating-Gate Programming Environment for System-Level ICs
3. An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications
4. Winner-Take-All Networks of O(N) Complexity
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