PLL-SAR: A New High-Speed Analog to Digital Converter Architecture
Author:
Affiliation:
1. Oregon State University,Corvallis,OR,97330
2. Oregon State University,Department of Electrical Engineering and Computer Science,Corvallis,OR,USA,97330
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10405424/10405847/10405967.pdf?arnumber=10405967
Reference7 articles.
1. A VCO Based Highly Digital Temperature Sensor With 0.034 °C/mV Supply Sensitivity
2. A Deterministic Digital Background Calibration Technique for VCO-Based ADCs
3. Linearization Through Dithering: A 50 MHz Bandwidth, 10-b ENOB, 8.2 mW VCO-Based ADC
4. A Highly Linear OTA-Less 1-1 MASH VCO-Based $\Delta\Sigma$ ADC With an Efficient Phase Quantization Noise Extraction Technique
5. A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-$\Delta\Sigma$ M Structure
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