A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-$\Delta\Sigma$ M Structure
Author:
Funder
National Science Foundation
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
https://ieeexplore.ieee.org/ielam/4/9011683/8945232-aam.pdf
Cited by 43 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
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2. A 1.25MHz Bandwidth 86.4dB SNDR third-order VCO-based ADC design;2024 4th International Conference on Electronics, Circuits and Information Engineering (ECIE);2024-05-24
3. A 99.8-dB SNDR 10kHz-BW Second-Order DT Delta-Sigma Modulator with Single OTA and Enhanced Noise-Coupling;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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