A 94.6dB-SNDR 50kHz-BW 1-1-1 MASH ADC Using OTA-FIA Based Integrators
Author:
Affiliation:
1. College of Information Science & Electronic Engineering, Zhejiang University,Hangzhou,Zhejiang,China,310027
Funder
National Key R&D Program of China
National Natural Science Foundation of China (NSFC)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181887.pdf?arnumber=10181887
Reference7 articles.
1. A 100kHz-Bandwidth 98.3dB-SNDR Noise-Shaping SAR ADC with Improved Mismatch Error Shaping and Speed-Up Techniques
2. A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation
3. A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs
4. Analysis and Design of a Discrete-Time Delta-Sigma Modulator Using a Cascoded Floating-Inverter-Based Dynamic Amplifier
5. 9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping
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1. Low‐power multibit delta–sigma modulator based on passive and unattenuated summation scheme;International Journal of Circuit Theory and Applications;2024-06-18
2. A 99.8-dB SNDR 10kHz-BW Second-Order DT Delta-Sigma Modulator with Single OTA and Enhanced Noise-Coupling;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. A 90.9 dB SNDR 95.3 dB DR Audio Delta–Sigma Modulator with FIA-Assisted OTA;Sensors;2024-02-23
4. A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL;Microelectronics Journal;2024-02
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