A Two-Phase Linear-Exponential Incremental ADC with Second-order Noise Coupling
Author:
Affiliation:
1. Shanghai Jiao Tong University,Department of Micro-Nano Electronics,Shanghai,China
2. University of Macau,State Key Laboratory of Analog and Mixed-Signal VLSI,Macao,China
Funder
National Key R&D Program of China
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10182049.pdf?arnumber=10182049
Reference21 articles.
1. A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over IMHz BW;wang;IEEE Asian Solid-State Circuits Conference (A-SSCC),0
2. A 1.25 MS/s Two-Step Incremental ADC With 100-dB DR and 110-dB SFDR
3. Incremental Delta-Sigma ADCs: A Tutorial Review
4. A Hybrid Continuous-Time Incremental and SAR Two-Step ADC With 90.5-dB DR Over 1-MHz BW
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