A Low-Distortion Power-Efficient Feedforward Technique for DT Delta-Sigma ADCs
Author:
Affiliation:
1. EECS Oregon State University,Corvallis,US
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181444.pdf?arnumber=10181444
Reference8 articles.
1. A 550-$\mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $\Sigma\Delta$ ADC With 256 Clock Cycles in 65-nm CMOS
2. A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT $\Delta\Sigma$ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer
3. A 0.5-V 35-$ \mu $W 85-dB DR Double-Sampled $\Delta\Sigma$ Modulator for Audio Applications
4. A 101 dB DR 1.1 mW audio delta-sigma modulator with direct-charge-transfer adder and noise shaping enhancement
5. A Second-Order Passive Noise-Shaping SAR ADC With 4× Passive Gain and A Two-Input-Pair Comparator
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 99.8-dB SNDR 10kHz-BW Second-Order DT Delta-Sigma Modulator with Single OTA and Enhanced Noise-Coupling;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
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