A side-channel resistant implementation of AES combining clock randomization with duplication
Author:
Affiliation:
1. Royal Institute of Technology (KTH),Department of Electrical Engineering,Stockholm,Sweden,196 40
2. Ericsson Research Security,Lund,Sweden,223 62
Funder
Vinnova
Swedish Civil Contingencies Agency
Swedish Research Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10181621.pdf?arnumber=10181621
Reference28 articles.
1. RFTC
2. Analysis and Improvement of the Random Delay Countermeasure of CHES 2009
3. UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks
4. Lightweight Side-Channel Protection using Dynamic Clock Randomization
5. An Efficient Method for Random Delay Generation in Embedded Software
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1. Attacking and Securing the Clock Randomization and Duplication Side-Channel Attack Countermeasure;Lecture Notes in Computer Science;2024
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