RFTC

Author:

Jayasinghe Darshana1,Ignjatovic Aleksandar1,Parameswaran Sri1

Affiliation:

1. School of Computer Science and Engineering, University of New South Wales, Sydney, Australia

Publisher

ACM

Reference22 articles.

1. Federal Information Processing Standards Publication 197 announcing the ADVANCED ENCRYPTION STANDARD (AES). 2001. Federal Information Processing Standards Publication 197 announcing the ADVANCED ENCRYPTION STANDARD (AES). 2001.

2. Altera. Altera I/O Phase-Locked Loop (Altera IOPLL) 2015. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-altera-iopll-15.0.pdf. Altera. Altera I/O Phase-Locked Loop (Altera IOPLL) 2015. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-altera-iopll-15.0.pdf.

3. Random clock against differential power analysis

4. Correlation Power Analysis with a Leakage Model

5. A Countermeasure against Differential Power Analysis based on Random Delay Insertion

Cited by 14 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Sensors for Remote Power Attacks: New Developments and Challenges;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

2. Spread Spectrum-Based Countermeasures for Cryptographic RISC-V SoC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

3. Attacking and Securing the Clock Randomization and Duplication Side-Channel Attack Countermeasure;Lecture Notes in Computer Science;2024

4. Protecting Parallel Data Encryption in Multi-Tenant FPGAs by Exploring Simple but Effective Clocking Methodologies;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024

5. FPGA-Patch: Mitigating Remote Side-Channel Attacks on FPGAs using Dynamic Patch Generation;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07

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