IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits
Author:
Affiliation:
1. Southeast University,National ASIC System Engineering Research Center,Nanjing,China,210096
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10181241/10181318/10182138.pdf?arnumber=10182138
Reference16 articles.
1. 8.2 Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic
2. LECTOR: a technique for leakage reduction in CMOS circuits
3. A 595pW 14pJ/Cycle microcontroller with dual-mode standard cells and self-startup for battery-indifferent distributed sensing
4. A fW- and kHz-Class Feedforward Leakage Self-Suppression Logic Requiring No External Sleep Signal to Enter the Leakage Suppression Mode
5. Leakage current reduction in CMOS VLSI circuits by input vector control
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. ARA-RCIV: Identifying Reliability-Critical Input Vectors of Logic Circuits Based on the Association Rules Analysis Approach;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture;IEEE Access;2024
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