A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set-Reference-Cited by-同舟云学术

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A fine-line NMOS 3-Gbit/s 12 channel time-division multiplexer-demultiplexer chip set

Published:1989-06 Issue:3 Volume:24 Page:814-821
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Bayruns R.J.,Hofstatter E.A.,Weston H.T.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx1/4/1390/00032044.pdf?arnumber=32044

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 12-ps-resolution digital variable-delay macro cell on GaAs 100 K-gates gate array using a meshed air bridge structure;IEEE Journal of Solid-State Circuits;1999

2. Time resolution of NMOS sampling switches used on low-swing signals;IEEE Journal of Solid-State Circuits;1998

3. The delay vernier pattern generation technique;IEEE Journal of Solid-State Circuits;1997-04

4. A 4:1 MUX Circuit Using 1/4 Micron CMOS/SIMOX for High-Speed and Low-Power Applications;Japanese Journal of Applied Physics;1996-02-28

5. A newly observed high frequency effect on the ESD protection utilized in a gigahertz NMOS technology;Journal of Electrostatics;1993-12

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