Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution-Reference-Cited by-同舟云学术

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Fault-Tolerant Systolic Array Based Accelerators for Deep Neural Network Execution

Published:2019-10 Issue:5 Volume:36 Page:44-53
ISSN:2168-2356
Container-title:IEEE Design & Test
language:
Short-container-title:IEEE Des. Test

Author:

Zhang Jeff Jun^ORCID,Basu Kanad^ORCID,Garg Siddharth^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/6221038/8855151/08709714.pdf?arnumber=8709714

Cited by 59 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Hybrid-Grained Pruning and Hardware Acceleration for Convolutional Neural Networks;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Highly Fault-Tolerant Systolic-Array-Based Matrix Multiplication;Electronics;2024-05-05

3. NN-ECC: Embedding Error Correction Codes in Neural Network Weight Memories using Multi-task Learning;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

4. Error Checking for Sparse Systolic Tensor Arrays;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

5. Improving GPU Reliability with Software-Managed Pipeline Parity for Error Detection and Correction;2024 IEEE 15th Latin America Symposium on Circuits and Systems (LASCAS);2024-02-27

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