Efficient VLSI implementation of modulo (2/sup n/±1) addition and multiplication-Reference-Cited by-同舟云学术

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Efficient VLSI implementation of modulo (2/sup n/±1) addition and multiplication

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Container-title:Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336)
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Author:

Zimmermann R.

Publisher

IEEE Comput. Soc

Link

http://xplorestaging.ieee.org/ielx5/6186/16513/00762841.pdf?arnumber=762841

Cited by 164 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Area-Power-Delay-Efficient Multi-Modulus Multiplier Based on Area-Saving Hard Multiple Generator Using Radix-8 Booth-Encoding Scheme on Field Programmable Gate Array;Electronics;2024-01-10

2. Optimal Moduli Searching for RNS-Based Devices;2023 International Conference on Electrical, Computer and Energy Technologies (ICECET);2023-11-16

3. A Generalized Residue Number System Design Approach for Ultralow-Power Arithmetic Circuits Based on Deterministic Bit-Streams;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-11

4. Design of reverse converters for the general RNS 3-moduli set {2k, 2n − 1, 2n + 1};EURASIP Journal on Advances in Signal Processing;2023-09-04

5. On the modulo 2 +1 addition and subtraction for weighted operands;Microprocessors and Microsystems;2023-09

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