A Multi-level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models-Reference-Cited by-同舟云学术

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A Multi-level Analog IC Design Flow for Fast Performance Estimation Using Template-based Layout Generators and Structural Models

Published:2022-06-12 Issue: Volume: Page:
ISSN:
Container-title:2022 18th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
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Author:

Prautsch Benjamin¹,Markwirth Thomas¹,Schenkel Frank²,Wittmann Reimund³,Eichler Uwe¹,Lienig Jens⁴

Affiliation:

1. Institute for Integrated Circuits,Division Engineering of Adaptive Systems,Fraunhofer IIS/EAS,Dresden,Germany

2. MunEDA GmbH,München,Germany

3. IMST GmbH,Kamp-Lintfort,Germany

4. Dresden University of Technology,Dresden,Germany

Funder

Ministry of Education

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816063/9816175/09816280.pdf?arnumber=9816280

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Automated Framework for Switched-Capacitor Power Amplifier Implementation Verified in 65 nm CMOS;2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD);2023-07-03

2. Routing buses impact analysis on the results on modeling standard digital cell on CMOS 28 nm;Modeling of systems and processes;2023-06-14

3. OpenFASOC: An Open Platform Towards Analog and Mixed-Signal Automation and Acceleration of Chip Design;2023 International Symposium on Devices, Circuits and Systems (ISDCS);2023-05-29

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