A high-speed clockless serial link transceiver
Author:
Publisher
IEEE Comput. Soc
Link
http://xplorestaging.ieee.org/ielx5/8538/26997/01199175.pdf?arnumber=1199175
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Analysis of Serializer for High Speed Transmission;2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience & Nanotechnology (5NANO);2022-04-28
2. A Clock-Less Ultra-Low Power Bit-Serial LVDS Link for Address-Event Multi-chip Systems;2018 24th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2018-05
3. Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link;2014 IEEE 44th International Symposium on Multiple-Valued Logic;2014-05
4. High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs;IEICE Transactions on Information and Systems;2014
5. Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs;Integration;2014-01
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