High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs-Reference-Cited by-同舟云学术

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High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs

Published:2014 Issue:6 Volume:E97.D Page:1546-1556
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

ONIZAWA Naoya¹,MOCHIZUKI Akira²,SHIRAHAMA Hirokatsu²,IMAI Masashi³,YONEDA Tomohiro⁴,HANYU Takahiro²

Affiliation:

1. Frontier Research Institute for Interdisciplinary Sciences, Tohoku University

2. Research Institute of Electrical Communication, Tohoku University

3. Dept. of Electronics and Information Technology, Hirosaki University

4. National Institute of Informatics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E97.D/6/E97.D_1546/_pdf

Reference32 articles.

1. [1] L. Benini and G.D. Micheli, “Networks on chips: A new SoC paradigm,” Computer, vol.35, no.1, pp.70-78, 2002.

2. [2] D. Lattard, E. Beigne, F. Clermidy, Y. Durand, R. Lemaire, P. Vivet, and F. Berens, “A reconfigurable baseband platform based on an asynchronous network-on-chip,” IEEE J. Solid-State Circuits, vol.43, no.1, pp.223-235, 2008.

3. [3] N. Onizawa, A. Matsumoto, T. Funazaki, and T. Hanyu, “High-throughput compact delay-insensitive asynchronous NoC router,” IEEE Trans. Comput., vol.63, no.3, pp.637-649, 2014.

4. [4] L. Plana, J. Bainbridge, S. Furber, S. Salisbury, Y. Shi, and J. Wu, “An on-chip and inter-chip communications network for the SpiNNaker massively-parallel neural net simulator,” Second ACM/IEEE International Symposium on Networks-on-Chip, pp.215-216, April 2008.

5. [5] T. Yoneda and M. Imai, “Dependable routing in multi-chip NoC platforms for automotive applications,” 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp.217-224, Oct. 2012.

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