An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator-Reference-Cited by-同舟云学术

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An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator

Published:2008-04 Issue: Volume: Page:
ISSN:
Container-title:Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)
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Author:

Plana Luis A.,Bainbridge John,Furber Steve,Salisbury Sean,Shi Yebin,Wu Jian

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/4492707/4492708/04492744.pdf?arnumber=4492744

Cited by 13 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

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2. A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems;IEEE Access;2024

3. Asynchronous Spiking Neurons, the Natural Key to Exploit Temporal Sparsity;IEEE Journal on Emerging and Selected Topics in Circuits and Systems;2019-12

4. Performance Comparison of Time-Step-Driven versus Event-Driven Neural State Update Approaches in SpiNNaker;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018-05

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