Uncle - An RTL Approach to Asynchronous Design
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/6242773/6243861/06243883.pdf?arnumber=6243883
Cited by 37 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Forward Body Biasing Techniques for Low Power Null Convention Logic in SOI;2024 Tenth International Conference on Communications and Electronics (ICCE);2024-07-31
2. A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits;Journal of Low Power Electronics and Applications;2024-01-14
3. Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-V;2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2023-08-28
4. Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits;International Journal of Electrical and Electronics Research;2023-03-30
5. Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits;IEEE Access;2023
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