Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors-Reference-Cited by-同舟云学术

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Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors

Published:2022-12-11 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Conference on Emerging Electronics (ICEE)
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Author:

Manikandan S.¹,Chauhan Nitanshu²,Bagga Navjeet³,Kumar Abhishek¹,Banchhor Shashank¹,Roy Sourajeet¹,Bulusu Anand¹,Dasgupta Avirup¹,Dasgupta Sudeb¹

Affiliation:

1. Indian Institute of Technology,Department of Electronics and Communication Engineering,Roorkee,Uttarkhand,India

2. National Institute of Technology,Department of Electronics Engineering,Uttarakhand,India

3. Indian Institute of Information Technology, Design and Manufacturing,Department of Electronics and Communication Engineering,Jabalpur

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10117590/10117577/10117608.pdf?arnumber=10117608

Reference22 articles.

1. Compact Model for Geometry Dependent Mobility in Nanosheet FETs

2. A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

3. BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs

4. Gate-All-Around FET Design Rule for Suppression of Excess Non-Linearity

5. Investigation of Gate Sidewall Spacer Optimization From OFF-State Leakage Current Perspective in 3-nm Node Device

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