A simple countermeasure to mitigate buffer overflow attack using minimalistic hardware-integrated software simulation for FPGA

Author:

Sayeeshwari S.1,Prabhu E.1

Affiliation:

1. Amrita Vishwa Vidyapeetham,Amrita School of Engineering, Coimbatore,Department of Electronics and Communications Engineering,India

Publisher

IEEE

Reference16 articles.

1. A Compiler-Hardware Technique for Protecting Against Buffer Overflow Attacks;leontie;Journal of Information Assurance and Security,2010

2. Hardware Trojan Detection using Supervised Machine Learning;gowtham;Proc 6th Int Conf Communication and Electronics Systems (ICCES-2021),2021

3. Hardware Trojan Detection using Ring Oscillator;deepthi;Proc 6th Int Conf Communication and Electronics Systems (ICCES-2021),2021

4. Vivado v2017.4,0

5. Reducing logic encryption overhead through gate level key insertion

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1. LsStk: Lightweight solution to preventing Stack from buffer overflow vulnerability;2023 17th International Conference on Open Source Systems and Technologies (ICOSST);2023-12-20

2. A Novel Circuit-Level Method for Hardware Trojan Detection in Digital Designs;2023 10th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2023-12-01

3. Detection of Hardware Trojan Horse using Unsupervised Learning Approach;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13

4. Error Resolving in SRAM Emulated FPGA using CRC;2023 Third International Conference on Secure Cyber Computing and Communication (ICSCCC);2023-05-26

5. A Survey on Hardware Security: Current Trends and Challenges;IEEE Access;2023

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