Reducing logic encryption overhead through gate level key insertion
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7515073/7527154/07538898.pdf?arnumber=7538898
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. GateLock: Input-Dependent Key-Based Locked Gates for SAT Resistant Logic Locking;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-02
2. Efficient design and analysis of secure CMOS logic through logic encryption;Scientific Reports;2023-01-20
3. Analog Security;Hardware Security Primitives;2022-10-12
4. A simple countermeasure to mitigate buffer overflow attack using minimalistic hardware-integrated software simulation for FPGA;2022 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT);2022-07-08
5. Flip-Flop-Based Approach for Logic Encryption Technique;Lecture Notes in Networks and Systems;2022
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