Author:
Cheng Hsiang-Yun,Lin Chung-Hsiang,Li Jian,Yang Chia-Lin
Cited by
18 articles.
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1. ROMA: A Reconfigurable On-chip Memory Architecture for Multi-core Accelerators;2023 IEEE International Conference on High Performance Computing & Communications, Data Science & Systems, Smart City & Dependability in Sensor, Cloud & Big Data Systems & Application (HPCC/DSS/SmartCity/DependSys);2023-12-17
2. AuRORA: Virtualized Accelerator Orchestration for Multi-Tenant Workloads;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28
3. MoCA: Memory-Centric, Adaptive Execution for Multi-Tenant Deep Neural Networks;2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2023-02
4. Elastic cloud services;Proceedings of the 13th Symposium on Cloud Computing;2022-11-07
5. Instruction Prefetch for Improving GPGPU Performance;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2021-05-01