Instruction Prefetch for Improving GPGPU Performance
Author:
Affiliation:
1. School of Software Technology, Dalian University of Technology
2. School of Computer Science and Technology, Dalian University of Technology
3. Jianghuai College of Ahui University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E104.A/5/E104.A_2020EAP1105/_pdf
Reference27 articles.
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2. [2] M. Gebhart, D.R. Johnson, D. Tarjan, S.W. Keckler, W.J. Dally, E. Lindholm, and K. Skadron, “Energy-efficient mechanisms for managing thread context in throughput processors,” 2011 38th Annual International Symposium on Computer Architecture (ISCA), pp.235-246, 2011. 10.1145/2000064.2000093
3. [3] H.Y. Cheng, C.H. Lin, J. Li, and C.L. Yang, “Memory latency reduction via thread throttling,” Proc. 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO'43, USA, p.53-64, IEEE Computer Society, 2010. 10.1109/micro.2010.39
4. [4] X. Chen, L.W. Chang, C.I. Rodrigues, J. Lv, Z. Wang, and W.M. Hwu, “Adaptive cache management for energy-efficient gpu computing,” Proc. 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-47, USA, pp.343-355, IEEE Computer Society, 2014. 10.1109/micro.2014.11
5. [5] W.W.L. Fung, I. Sham, G. Yuan, and T.M. Aamodt, “Dynamic warp formation and scheduling for efficient GPU control flow,” 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), pp.407-420, 2007. 10.1109/micro.2007.4408272
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