Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9424228/9424248/09424349.pdf?arnumber=9424349
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Congestion-Aware Vertical Link Placement and Application Mapping Onto 3-D Network-on-Chip Architectures;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-08
2. Dynamic Precision-Scalable Thermal Mapping Algorithm for Three Dimensional Systolic-Array Based Neural Network Accelerator;IEEE Transactions on Consumer Electronics;2024-02
3. TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
4. Temperature-Prediction Based Rate-Adjusted Time and Space Mapping Algorithm for 3D CNN Accelerator Systems;IEEE Transactions on Computers;2023-10
5. Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
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