Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN Workloads
Author:
Affiliation:
1. Boston University
2. Advanced Micro Devices
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10136870/10136706/10137047.pdf?arnumber=10137047
Reference26 articles.
1. A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim
2. Thermal-aware design space exploration of 3D systolic ML accelerators;mathur;IEEE JxCDC,2021
3. Empowering things with intelligence: a survey of the progress, challenges, and opportunities in artificial intelligence of things;zhang;IEEE IoT,2020
4. Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. TREAD-M3D: Temperature-Aware DNN Accelerators for Monolithic 3-D Mobile Systems;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
2. NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3D-Stacked-DRAM;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023
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