A programmable dynamic interconnection network router with hidden refresh
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx4/81/15832/00735440.pdf?arnumber=735440
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. RETRACTED: Design of 8-bit Dynamic CMOS Priority Resolvers based on Active- High and Active-Low Logic;WSEAS TRANSACTIONS ON INFORMATION SCIENCE AND APPLICATIONS;2021-12-30
2. Ultra-low-power and compact 8-bit CMOS priority encoder;International Journal of Electronics Letters;2016-06-16
3. Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture;2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST);2016-05
4. Calculation of Average Power, Leakage Power, and Leakage Current of FinFET Based 4-Bit Priority Encoder;2015 Fifth International Conference on Advanced Computing & Communication Technologies;2015-02
5. Calculation of Power Delay Product and Energy Delay Product in 4-Bit FinFET Based Priority Encoder;Springer Proceedings in Physics;2015
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