A 1-Mbit CMOS DRAM with fast page mode and static column mode-Reference-Cited by-同舟云学术

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A 1-Mbit CMOS DRAM with fast page mode and static column mode

Published:1985-10 Issue:5 Volume:20 Page:903-908
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Saito S.,Fujii S.,Okada Y.,Shinozaki S.,Natori K.,Ozawa O.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/22604/01052413.pdf?arnumber=1052413

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High Signal-to-Noise Ratio DRAM Design and Technology;VLSI Memory Chip Design;2001

2. PELOX integrated PBL;IEEE Transactions on Semiconductor Manufacturing;1993

3. Substrate-voltage control circuits for DRAMs at power-on timing;Electronics and Communications in Japan (Part II: Electronics);1992

4. Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM;IEEE Journal of Solid-State Circuits;1990-04

5. Low Pressure Deposition of Doped SiO2 by Pyrolysis of Tetraethylorthosilicate (TEOS): II . Arsenic Doped Films;Journal of The Electrochemical Society;1989-10-01

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