Substrate-voltage control circuits for DRAMs at power-on timing-Reference-Cited by-同舟云学术

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Substrate-voltage control circuits for DRAMs at power-on timing

Published:1992 Issue:8 Volume:75 Page:54-62
ISSN:8756-663X
Container-title:Electronics and Communications in Japan (Part II: Electronics)
language:en
Short-container-title:Electron. Comm. Jpn. Pt. II

Author:

Miyamoto Hiroshi,Suwa Makoto,Tokami Kenji,Yamada Michihiro

Publisher

Wiley

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,General Physics and Astronomy

Reference11 articles.

1. A 5 V-only 64K dynamic RAM based on high S/N design

2. Fully boosted 64K dynamic RAM with automatic and self-refresh

3. A 1-Mbit CMOS DRAM with fast page mode and static column mode

4. , , , , and . A 20-ns static column, 1-Mbit DRAM in CMOS technology. ISSCC Dig. Tech. Papers, pp. 254–255 (Feb. 1985).

5. A 50-μA standby 1M x 1/256K×4 CMOS DRAM with high-speed sense amplifier

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