ASIC design of MUL-RED Radix-2 Pipeline FFT circuit for 802.11ah system
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7500233/7503660/07503678.pdf?arnumber=7503678
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. DRRA-based Reconfigurable Architecture for Mixed-Radix FFT;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01
2. Hardware Implementation of CORDIC Based Physical Layer Phase Decryption for IEEE 802.11ah;Proceedings of the 7th International Conference on Communications and Broadband Networking - ICCBN 2019;2019
3. Low-power and high-throughput 128-point feedforward FFT processor;Cluster Computing;2018-02-26
4. Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays;Journal of Signal Processing Systems;2018-02-01
5. An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications;Integration;2017-03
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