Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays-Reference-Cited by-同舟云学术

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Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays

Published:2018-02-01 Issue:5 Volume:91 Page:459-473
ISSN:1939-8018
Container-title:Journal of Signal Processing Systems
language:en
Short-container-title:J Sign Process Syst

Author:

Shami Muhammad Ali^ORCID,Tajammul Muhammad Adeel,Hemani Ahmed

Funder

Vetenskapsrådet

Huaewi ICT

Higher Education Commission, Pakistan

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Modeling and Simulation,Information Systems,Signal Processing,Theoretical Computer Science,Control and Systems Engineering

Link

http://link.springer.com/article/10.1007/s11265-017-1326-7/fulltext.html

Reference36 articles.

1. Zyren, J. (2007). Overview of the 3gpp long term evolution physical layer. Technical Report 3GPPEVOLUTIONWP, Freescale 07.

2. Shami, M. A., & Hemani, A. (2010). Control scheme for a cgra. In Proceedings of the 22nd international computer architecture and high performance computing (SBAC-PAD) symposium. https://doi.org/10.1109/SBAC-PAD.2010.12 (pp. 17–24).

3. Loomis, H., Kragh, F., & Dinolt, G. (2015). Implementing a software defined radio using the maestro 49-tile processor. In 2015 IEEE aerospace conference. https://doi.org/10.1109/AERO.2015.7119153 (pp. 1–14).

4. Tran, T. H., Kanagawa, S., Nguyen, D. P., & Nakashima, Y. (2016). Asic design of mul-red radix-2 pipeline fft circuit for 802.11ah system. In 2016 IEEE symposium in low-power and high-speed chips (COOL CHIPS XIX). https://doi.org/10.1109/CoolChips.2016.7503678 (pp. 1–3).

5. Yu, C., Yen, M.-H., Hsiung, P.-A., & Chen, S.-J. (2011). A low-power 64-point pipeline fft/ifft processor for ofdm applications. IEEE Transactions on Consumer Electronics, 57(1), 40–40. https://doi.org/10.1109/TCE.2011.5735479 . ISSN 0098-3063.

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