A 13-bit Radiation-Hardened SAR-ADC with Error Correction by Adaptive Topology Transformation

Author:

Aoki Yuya1,Iwata Tatsuya1,Miki Takuji2,Kobayashi Kazutoshi3,Yoshikawa Takefumi1

Affiliation:

1. Graduate School of Engineering, Toyama Prefectural University,Imizu,Toyama,Japan,939-0398

2. Graduate School of Science, Technology and Innovation, Kobe University,Kobe,Hyogo,Japan,657-8501

3. Graduate School of Science and Technology, Kyoto Institute of Technology,Hashigami,Kyoto,Japan,606-8585

Publisher

IEEE

Reference15 articles.

1. A Low-Power Radiation-Hardened Flip-Flop with Stacked Transistors in a 65 nm FDSOI Process

2. Hardness-by-design approach for 0.15 /spl mu/m fully depleted CMOS/SOI digital logic devices with enhanced SEU/SET immunity

3. Analysis of single-event effects in a radiation-hardened low-jitter PLL under heavy ion and pulsed laser irradiation;chen;IEEE Trans Nucl Sci,2016

4. A Bit-Error Rate Measurement and Error Analysis of Wireline Data Transmission using Current Source Model for Single Event Effect under Irradiation Environment

5. Analysis of single-event effects in a radiation-hardened low-jitter PLL under heavy ion and pulsed laser irradiation;chen;IEEE Trans Nucl Sci,2016

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