Effects of Collected Charge and Drain Area on SE Response of SRAMs at the 5-nm FinFET Node
Author:
Affiliation:
1. Vanderbilt University,Department of ECE,Nashville,TN,USA,37212
2. Synopsys, Inc.,Mountain View,CA,USA,94043
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117589/10117581/10118115.pdf?arnumber=10118115
Reference22 articles.
1. Novel SER standards: Backgrounds and methodologies
2. Predicting the vulnerability of memories to muon-induced SEUs with low-energy proton tests informed by Monte Carlo simulations
3. The Effects of Neutron Energy and High-Z Materials on Single Event Upsets and Multiple Cell Upsets
4. The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction
5. Neutron-Induced Charge Collection Simulation of Bulk FinFET SRAMs Compared With Conventional Planar SRAMs
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Multiple Bit Upsets in Register Circuits at the 5-nm Bulk FinFET Node;2024 IEEE International Reliability Physics Symposium (IRPS);2024-04-14
2. Temperature Dependence of Critical Charge and Collected Charge in 5-nm FinFET SRAM;IEEE Transactions on Nuclear Science;2023
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