Pattern Generation for Efficient Acceptability Verification of Approximate Circuits
Author:
Affiliation:
1. National Sun Yat-sen University,Department of Electrical Engineering,Taiwan
2. Institute of Computer Architecture and Computer Engineering, University of Stuttgart,Germany
Funder
German Research Foundation (DFG)
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10546337/10546338/10546386.pdf?arnumber=10546386
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1. Coverage-directed test generation through automatic constraint extraction
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4. Analysis and Evaluation of Image Quality Metrics
5. Precise error determination of approximated components in sequential circuits with model checking
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