Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications-Reference-Cited by-同舟云学术

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Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Published:2020 Issue: Volume:8 Page:711-715
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

Saadat Ali^ORCID,Van De Put Maarten L.^ORCID,Edwards Hal,Vandenberghe William G.^ORCID

Funder

Texas Instruments Inc.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology

Link

http://xplorestaging.ieee.org/ielx7/6245494/8949832/09137310.pdf?arnumber=9137310

Cited by 16 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of varying channel length on Analog/RF performances in a novel n-type silicon-based DG-JLT;Micro and Nanostructures;2024-09

2. Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications;Transactions on Electrical and Electronic Materials;2024-04-04

3. Superior Impact Ionization Rate in Deep Gate LDMOS Devices to Improve the Figure of Merit and Lattice Temperature;Journal of Electronic Materials;2023-12-04

4. Bulk-fin field-effect transistor-based capacitorless dynamic random-access memory and its immunity to the work-function variation effect;Japanese Journal of Applied Physics;2023-01-10

5. Algorithmic Optimization of Transistors Applied to Silicon LDMOS;IEEE Access;2023

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