Superior Impact Ionization Rate in Deep Gate LDMOS Devices to Improve the Figure of Merit and Lattice Temperature
Author:
Publisher
Springer Science and Business Media LLC
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s11664-023-10824-w.pdf
Reference24 articles.
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2. Y. Fan, X. Luo, K. Zhou, Y. Fan, Y. Jiang, Q. Wang, P. Wang, Y. Luo, and B. Zhang, An L-shaped low on-resistance current path SOI LDMOS with dielectric field enhancement. J. Semicond. 35, 034011 (2014). https://doi.org/10.1088/1674-4926/35/3/034011.
3. T. Erlbacher, Lateral Power Transistors in Integrated Circuits (Berlin: Springer, 2014).
4. Z. Dong, B. Duan, C. Fu, H. Guo, Z. Cao, and Y. Yang, Novel LDMOS optimizing lateral and vertical electric field to improve breakdown voltage by multi-ring technology. IEEE Electron. Device Lett. 39, 1424 (2018). https://doi.org/10.1109/LED.2018.2854417.
5. A. Saadat, M.L. Van De Put, H. Edwards, and W.G. Vandenberghe, Channel length optimization for planar LDMOS field-effect transistors for low-voltage power applications. IEEE J. Electron Devices Soc 8, 1450 (2020). https://doi.org/10.1109/JEDS.2020.3008388.
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