Area-Efficient Power-Rail ESD Clamp Circuit With False-Trigger Immunity in 28nm CMOS Process
Author:
Affiliation:
1. Key Laboratory of Microelectronic Devices and Circuits, School of Integrated Circuits, Peking University, Beijing, China
2. FPGA Department, Beijing Microelectronics Technology Institute, Beijing, China
Funder
Project of State Grid Corporation of China in 2019
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials,Biotechnology
Link
http://xplorestaging.ieee.org/ielx7/6245494/9714452/09858072.pdf?arnumber=9858072
Reference25 articles.
1. Low-Leakage and Variable V HOLD Power Clamp for Wide Stress Time Range From ESD to Surge Test
2. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI;ker;IEEE Trans Electron Devices,1999
3. A low-leakage, hybrid ESD power supply clamp in 65nm CMOS technology
4. An Area-Efficient Clamp Based on Transmission Gate Feedback Technology for Power Rail Electrostatic Discharge Protection
5. Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
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1. A Simulation Study of Bipolar I-MOS for ESD Protection;IEEE Transactions on Electron Devices;2023-12
2. A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance;Micromachines;2023-05-31
3. Gate Grounded Trench I-MOS as an ESD Clamp for Sub-2V Applications;IEEE Access;2023
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