Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles-Reference-Cited by-同舟云学术

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Reduction of Low Frequency Noise of Buried Channel PMOSFETs With Retrograde Counter Doping Profiles

Published:2024 Issue: Volume:12 Page:534-540
ISSN:2168-6734
Container-title:IEEE Journal of the Electron Devices Society
language:
Short-container-title:IEEE J. Electron Devices Soc.

Author:

Fujii Shuntaro¹^ORCID,Sakamoto Toshiro²^ORCID,Morita Soichi³^ORCID,Miyazaki Tsutomu⁴^ORCID

Affiliation:

1. Product Platform Technology Group, Asahi Kasei Microdevices Corporation, Yokohama, Kanagawa, Japan

2. Device & Process Application Development Unit, Asahi Kasei Microdevices Corporation, Yokohama, Kanagawa, Japan

3. Procurement Department, Asahi Kasei Microdevices Corporation, Chiyoda-ku, Tokyo, Japan

4. Quality Management Department, Asahi Kasei Microdevices Corporation, Nobeoka, Miyazaki, Japan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx8/6245494/10416702/10601688.pdf?arnumber=10601688

Reference36 articles.

1. Impact of random telegraph noise on CMOS logic delay uncertainty under low voltage operation

2. Random Telegraph Signal in CMOS Image Sensor Pixels

3. Noise Performance Improvements of 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Non-doped Pixel-FinFETs

4. RTN impact on data-retention failure/recovery in scaled (∼1Ynm) TLC NAND flash memories

5. Correlation between 1/fnoise and interface state density at the Fermi level in field‐effect transistors

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