Output load capacitance based low power implementation of UART on FPGA-Reference-Cited by-同舟云学术

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Output load capacitance based low power implementation of UART on FPGA

Published:2014-01 Issue: Volume: Page:
ISSN:
Container-title:2014 International Conference on Computer Communication and Informatics
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Author:

Singh P R,Pandey B,Kumar T,Das T,Om Jee Pandey

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6915233/6921705/06921826.pdf?arnumber=6921826

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design of Multi-Serial Port Controller based on PCIe;2023 3rd International Conference on Electronic Information Engineering and Computer Communication (EIECC);2023-12-22

2. Design of 4-bit absolute-value detector with trade-off between propagation delay and energy consumption;AIP Conference Proceedings;2023

3. Design of Energy Efficient IoMT Electrocardiogram (ECG) Machine on 28 nm FPGA;Studies in Big Data;2023

4. Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA;Wireless Personal Communications;2018-05-08

5. Input–Output Standard-Based Energy Efficient UART Design on 90 nm FPGA;System and Architecture;2018

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