AI-based Timing Error Modelling: A Case Study on a Pipelined Floating-point Core
Author:
Affiliation:
1. Queen’s University,Institute of Electronics, Communications and Information Technology,Belfast,UK
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10461386/10461450/10461477.pdf?arnumber=10461477
Reference5 articles.
1. Underdesigned and Opportunistic Computing in Presence of Hardware Variability
2. CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units
3. DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic Search
4. LEVAX: An Input-Aware Learning-Based Error Model of Voltage-Scaled Functional Units
5. Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations
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