Application - Hardware Co-Optimization of Crossbar-Based Neuromorphic Systems
Author:
Affiliation:
1. Mathematics and Computer Science Division, Argonne National Laboratory,Lemont,IL
2. Computing and Computational Sciences Directorate, Oak Ridge National Laboratory,Oak Ridge,TN
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10459339/10459727/10460051.pdf?arnumber=10460051
Reference33 articles.
1. Neuromorphic electronic systems
2. TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip
3. A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs)
4. A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons
5. eNVM RRAM reliability performance and modeling in 22FFL FinFET technology
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