Author:
Azizimazreah Arash,Chen Lizhong
Cited by
34 articles.
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1. High-Performance Hardware Acceleration Architecture for Cross-Silo Federated Learning;IEEE Transactions on Parallel and Distributed Systems;2024-08
2. Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms;2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA);2024-06-29
3. Algorithm/Hardware Co-Optimization for Sparsity-Aware SpMM Acceleration of GNNs;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-12
4. Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators;Proceedings of the 50th Annual International Symposium on Computer Architecture;2023-06-17
5. ViA: A Novel Vision-Transformer Accelerator Based on FPGA;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022-11