Inter-layer Scheduling Space Definition and Exploration for Tiled Accelerators

Author:

Cai Jingwei1ORCID,Wei Yuchen1ORCID,Wu Zuotong2ORCID,Peng Sen3ORCID,Ma Kaisheng1ORCID

Affiliation:

1. Institute for Interdisciplinary Information Sciences, Tsinghua University, Beijing, China

2. Xi'an Jiaotong University, Xi'an, China

3. Department of Electronics and Informatics School of Electronic Science and Engineering, Xi'an Jiaotong University, Xi'an, China

Funder

National Key Research and Development Program of China

Key Research and Development Program of Shaanxi

Publisher

ACM

Reference64 articles.

1. [n. d.]. Calculation of Our Inter-layer Space Size. https://github.com/SET-ISCA2023/Tile-Alloc-Algorithm/blob/master/Space_Size_Calculation.pdf. [n. d.]. Calculation of Our Inter-layer Space Size. https://github.com/SET-ISCA2023/Tile-Alloc-Algorithm/blob/master/Space_Size_Calculation.pdf.

2. [n. d.]. The Optimal Tile Allocation Algorithm. https://github.com/SET-ISCA2023/Tile-Alloc-Algorithm/blob/master/Optimal_Tile_Allocation_Algorithm.pdf. [n. d.]. The Optimal Tile Allocation Algorithm. https://github.com/SET-ISCA2023/Tile-Alloc-Algorithm/blob/master/Optimal_Tile_Allocation_Algorithm.pdf.

3. Fused-layer CNN accelerators

4. Apple. [n. d.]. Apple A15 Bionic. https://en.wikipedia.org/wiki/Apple_A15 . Apple. [n. d.]. Apple A15 Bionic. https://en.wikipedia.org/wiki/Apple_A15.

5. ARM. [n. d.]. ARM Artisan. https://developer.arm.com/downloads-beta/search?term=artisan. ARM. [n. d.]. ARM Artisan. https://developer.arm.com/downloads-beta/search?term=artisan.

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