Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability

Author:

Cardoso Maicon,Bubolz Andrei,Cortadella Jordi,Rosa Leomar,Marques Felipe

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. TransPlace: A Scalable Transistor-Level Placer for VLSI Beyond Standard-Cell-Based Design;2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC);2024-01-22

2. Routing buses impact analysis on the results on modeling standard digital cell on CMOS 28 nm;Modeling of systems and processes;2023-06-14

3. Models in the Process of Designing Complex Microelectronic Objects under Conditions of Uncertainty;2023 XXVI International Conference on Soft Computing and Measurements (SCM);2023-05-24

4. Transistor Reordering for Electrical Improvement in CMOS Complex Gates;2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design (SBCCI);2022-08-22

5. Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

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