A Systolic Dataflow Based Accelerator for CNNs

Author:

Das Saptarsi,Roy Arnab,Chandrasekharan Kiran Kolar,Deshwal Ankur,Lee Sehwan

Publisher

IEEE

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Scratchpad Memory Management for Deep Learning Accelerators;Proceedings of the 53rd International Conference on Parallel Processing;2024-08-12

2. EWS: An Energy-Efficient CNN Accelerator With Enhanced Weight Stationary Dataflow;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07

3. ACES: Accelerating Sparse Matrix Multiplication with Adaptive Execution Flow and Concurrency-Aware Cache Optimizations;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3;2024-04-27

4. Optimizing FPGA-Based DCN Accelerator with On-Chip Dataflow Reordering and Serial-Parallel Computing Array;2023 International Conference on High Performance Big Data and Intelligent Systems (HDIS);2023-12-06

5. A Survey of Design and Optimization for Systolic Array-based DNN Accelerators;ACM Computing Surveys;2023-08-25

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